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PLL205-13 motherboard clock generator for amd - k7 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 06/23/00 page 1 features generates all clock frequencies for via k7 chip sets requiring multiple cpu clocks and high speed sdram buffers. support one pair of differential cpu clocks, one 3.3v push-pull cpu, 6 pci and 13 high-speed sdram buffers for 3-dimm applications. one 24_48mhz clock and one 48mhz clock. two14.318mhz reference clocks. power management control to stop cpu, and power down mode from i2c programming. support 2-wire i2c serial bus interface with built- in vendor id, device id and revision id. single byte micro-step linear frequency progra- mming via i2c with glitch free smooth switching. enhanced cpu and sdram output drive selected by i2c. built-in programmable watchdog timer up to 63 seconds with 1-second interval. it will generate a low reset output when timer expired. spread spectrum 0.25% center spread, 0 to -0.5% down spread. available in 300 mil 48 pin ssop. block diagram pin configuration note: ^ : pull up, # : active low * : bi-directional latched at power-up i/o mode configuration mode (pin 7) pin 2 1 (output) ref0 0 (input) cpu_stop power group vdd0: pll core vdd1: ref(0:1), xin, xout vdd2: pci(0:5) vdd3: sdram(0:12) vdd4: 48mhz, 24_48mhz key specifications cpu cycle to cycle jitter: 250ps. pci to pci output skew: 500ps. cpu to cpu output skew: 175ps sdram to sdram output skew: 250ps. cpu to pci skew (cpu leads): 0 ~ 3 ns. sdram12 gnd sdram0 sdram1 vdd3 sdram2 sdram3 gnd sdram4 sdram5 sdata 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PLL205-13 gnd cput1 gnd cpuc0 cput0 vdd3 vdd3 sdram6 sdram7 vdd4 sclk gnd sdramin vdd2 gnd vdd1 xout xin gnd vdd0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 pci2 pci3 pci4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 sdram8 sdram9 vdd3 sdram11 gnd sdram10 pd/wdreset# ref1/fs2*^ ref0//cpu_stop#^ pci5/mode*^ pci1/sel24_48*^ pci0/fs3*^ 24_48mhz/fs1*^ 48mhz/fs0*^ watch dog vdd2 pci(0:4) pci5 cput0 cpuc0 control logic sdata sclk i2c logic vdd1 ref(0:1) xin xout xtal osc sdram(0:11) vdd3 sdram12 fs (0:3)* pll1 sst pll2 pd 48mhz vdd4 24_48mhz sdramin ? 2 cput1 wdreset
PLL205-13 motherboard clock generator for amd - k7 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 06/23/00 page 2 pin descriptions name number type description vdd0 1 p power supply for pll core. vdd1 6 p power supply for ref0, ref1, and crystal oscillator. vdd2 14 p power supply for pci (0:5). vdd3 19,30,36,42 p power supply for sdram (0:12). vdd4 27 p power supply for 24_48mhz and 48mhz. gnd 3,9,16,22, 33,39,45,47 p ground. xin 4 i 14.318mhz crystal input that has internal loads cap (36pf) and feedback resistor from xout. xout 5 o 14.318mhz crystal output. it has internal load cap (36pf). ref0//cpu_stop 2 b multiplexed pin controlled by mode signal. when cpu_stop is low, it will halt cput (0:1), cpuc0 and sdram (0:11) outputs. in output mode, this pin will generate buffered reference clock output. pci5/mode 7 b at power-up, mode function will be activated. when mode is low, pin 2 is input for cpu_stop. when high, pin 2 is output for ref0. after input data latched, this pin will generate pci bus clock. pci0/fs3 8 b at power-up, this pin is input pin and will determine cpu clock frequency. after input sampling, this pin will generate output clocks. fs3 has internal pull up (high by default). pci1/sel24_48 10 b at power-up, this pin will select 24mhz (when high) or 48mhz (when low) for pin25 output. after input sampling, this pin is pci output. it has internal pull up resistor. pci(2:4) 11,12,13 o pci clock outputs. sdramin 15 i buffer input pin: the signal provided to this input pin is buffered to 13 sdram outputs. sdram(0:11) 17,18,20,21, 28,29,31,32, 34,35,37,38 o sdram clock outputs, fan-out buffer outputs from sdramin pin. sdata 23 b sclk 24 i serial data inputs for serial interface port. 24_48mhz/fs1, 24mhz/fs0 25,26 b at power-up, these pins are input pins and will determine the cpu clock frequency. fs0, fs1 have internal pull up (high by default). sdram12 40 o when cpu_stop is low, this pin is still free running. when the power down is low, this sdram will be stopped. pd/wdreset 41 b power down control input. when low, power down will disable all clock outputs including internal vco and crystal clock. the enable of the watchdog timer masks the pd action. cput0 43 o ?true? clock of differential pair open-drain cpu output. cpuc0 44 o ?complementary? clocks of differential pair open-drain cpu outputs. cput1 46 o ?true? clock of push-pull cpu output. ref1/fs2 48 b buffered reference clock output after input data latched during power-up.
PLL205-13 motherboard clock generator for amd - k7 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 06/23/00 page 3 power management cpu_stop cpuc0 cput (0:1) sdram (0:11) sdram12 crystal vco 0 stopped low stopped low stopped low running running running 1 running running running running running running frequency ( mhz) selection table i2c byte0 bit2 fs3 fs2 fs1 fs0 cpu pci spread spectrum modulation 0 0 0 0 124.0 41.3 0.25% 0 0 0 1 75.0 37.5 0.25% 0 0 1 0 83.3 41.7 0.25% 0 0 1 1 66.8 33.4 0.25% 0 1 0 0 103.0 34.3 0.25% 0 1 0 1 112.0 37.3 0.25% 0 1 1 0 133.3 44.4 0.25% 0 1 1 1 100.0 33.3 0.25% 1 0 0 0 120.0 40.0 0.25% 1 0 0 1 115.0 38.3 0.25% 1 0 1 0 110.0 36.7 0.25% 1 0 1 1 105.0 35.0 0.25% 1 1 0 0 140.0 35.0 0.25% 1 1 0 1 150.0 37.5 0.25% 1 1 1 0 124.0 31.0 0.25% 0 default 1 1 1 1 133.3 33.3 0.25% 0 0 0 0 90.0 30.0 0.25% 0 0 0 1 92.5 30.8 0.25% 0 0 1 0 95.0 31.7 0.25% 0 0 1 1 97.5 32.5 0.25% 0 1 0 0 101.5 33.8 0.25% 0 1 0 1 127.0 42.3 0.25% 0 1 1 0 136.5 34.1 0.25% 0 1 1 1 100.0 33.3 0 to -0.5% 1 0 0 0 120.0 40.0 0 to -0.5% 1 0 0 1 117.5 39.2 0.25% 1 0 1 0 122.0 40.7 0.25% 1 0 1 1 107.5 35.8 0.25% 1 1 0 0 145.0 36.3 0.25% 1 1 0 1 155.0 38.7 0.25% 1 1 1 0 130.0 32.5 0.25% 1 1 1 1 1 133.3 33.3 0 to -0.5%
PLL205-13 motherboard clock generator for amd - k7 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 06/23/00 page 4 i2c bus configuration setting address assignment a6 a5 a4 a3 a2 a1 a0 r/w 1 1 0 1 0 0 1 _ slave receiver/transmitter provides both slave write and readback functionality data transfer rate standard mode at 100kbits/s serial bits reading the serial bits will be read or sent by the clock driver in the following order byte 0 ? bits 7, 6, 5, 4, 3, 2, 1, 0 byte 1 ? bits 7, 6, 5, 4, 3, 2, 1, 0 - byte n ? bits 7, 6, 5, 4, 3, 2, 1, 0 data protocol this serial protocol is designed to allow both blocks write and read from the controller. the bytes must be accessed in sequential order from lowest to highest byte. each byte transferred must be followed by 1 acknowledge bit. a byte transferred without acknowledged bit will terminate the transfer. the write or read block both begins with the master sending a slave address and a write condition (0xd2) or a read condition (0xd3). following the acknowledge of this address byte, in write mode: the command byte and byte count byte must be sent by the master but ignored by the slave, in read mode: the byte count byte will be read by the master then all other data byte . byte count byte default at power-up is = (0x09). i2c control registers 1. byte 0: functional and frequency select clock register (1=enable, 0=disable) bit pin# default description bit 7 8 0 fs3 ( see frequency selection table ) bit 6 48 1 fs2 ( see frequency selection table ) bit 5 25 0 fs1 ( see frequency selection table ) bit 4 26 0 fs0 ( see frequency selection table ) bit 3 - 0 frequency selection control bit 1=via i2c, 0=via external jumper bit 2 - 0 fs4 ( see frequency selection table ) bit 1 - 1 0=normal 1=spread spectrum enable bit 0 - 0 0=normal 1=tristate mode for all outputs
PLL205-13 motherboard clock generator for amd - k7 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 06/23/00 page 5 2. byte 1: cpu clock register (1=enable, 0=disable) bit pin# default description bit 7 - 1 reserved bit 6 17,18,20,21, 28,29,31,32, 34,35,37,38 1 high strength sdram select ( 1=normal, 0= enhanced by 25% ) bit 5 46 1 enhanced cput1 drive select ( 1=normal, 0=enhanced by 25% ) bit 4 43,44 1 enhanced cput0, cpuc0 drive s elect ( 1=normal, 0=enhanced by 25% ) bit 3 40 1 sdram12 ( active/inactive ) bit 2 - 1 reserved bit 1 43,44 1 cput0, cpuc0 ( active/inactive ) bit 0 46 1 cput1 ( active/inactive ) 3. byte 2: pci clock register (1=enable, 0=disable) bit pin# default description bit 7 - 1 reserved bit 6 7 1 pci5 ( active/inactive ) bit 5 - 1 reserved bit 4 13 1 pci4 ( active/inactive ) bit 3 12 1 pci3 ( active/inactive ) bit 2 11 1 pci2 ( active/inactive ) bit 1 10 1 pci1 ( active/inactive ) bit 0 8 1 pci0 ( active/inactive ) 4. byte 3: sdram clock register (1=enable, 0=disable) bit pin# default description bit 7 - 1 reserved bit 6 - 1 reserved bit 5 26 1 48mhz ( active/inactive ) bit 4 25 1 24_48mhz ( active/inactive ) bit 3 17 1 sdram11 ( active/inactive ) bit 2 18 1 sdram10 ( active/inactive ) bit 1 20 1 sdram9 ( active/inactive ) bit 0 21 1 sdram8 ( active/inactive )
PLL205-13 motherboard clock generator for amd - k7 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 06/23/00 page 6 5. byte 4: sdram clock register (1=enable, 0=disable) bit pin# default description bit 7 28 1 sdram7 ( active/inactive ) bit 6 29 1 sdram6 ( active/inactive ) bit 5 31 1 sdram5 ( active/inactive ) bit 4 32 1 sdram4 ( active/inactive ) bit 3 34 1 sdram3 ( active/inactive ) bit 2 35 1 sdram2 ( active/inactive ) bit 1 37 1 sdram1 ( active/inactive ) bit 0 38 1 sdram0 ( active/inactive ) 6. byte 5: peripheral clock register (1=enable, 0=disable) bit pin# default description bit 7 - x inverted power-up latched fs3 value (read only) bit 6 - x inverted power-up latched fs2 value (read only) bit 5 - x inverted power-up latched fs1 value (read only) bit 4 - x inverted power-up latched fs0 value (read only) bit 3 - 1 reserved bit 2 - x inverted power-up latched sel24_48mhz value (read only) bit 1 48 1 ref1 ( active/inactive ) bit 0 2 1 ref0 ( active/inactive ) 7. byte 6: fall-back frequency / revision / vendor id register (1=enable, 0=disable) bit pin# default description bit 7 - 0 wdt fall-back frequency selection for fs4 revision id bit 3* bit 6 - 0 wdt fall-back frequency selection for fs3 revision id bit 2* bit 5 - 0 wdt fall-back frequency selection for fs2 revision id bit 1* bit 4 - 0 wdt fall-back frequency selection for fs1 revision id bit 0* bit 3 - 0 wdt fall-back frequency selection for fs0 vendor id bit 3* bit 2 - 0 vendor id bit 2* bit 1 - 1 vendor id bit 1* bit 0 - 1 vendor id bit 0* note: *: default value at power-up
PLL205-13 motherboard clock generator for amd - k7 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 06/23/00 page 7 8. byte 7: linear programming (m) register (1=enable, 0=disable) bit pin# default description bit 7 - 0* linear programming sign bit ( 0 is ? + ?, 1 is ? - ? ) bit 6 - 0* linear programming magnitude bit 6 (msb) bit 5 - 0* linear programming magnitude bit 5 bit 4 - 0* linear programming magnitude bit 4 bit 3 - 0* linear programming magnitude bit 3 bit 2 - 0* linear programming magnitude bit 2 bit 1 - 0* linear programming magnitude bit 1 bit 0 - 0* linear programming magnitude bit 0 (lsb) note: this register will be initialized to 0 following watchdog reset. 9. byte 8: watchdog timer / device id register (1=enable, 0=disable) bit pin# default description bit 7 - 0 watchdog timer enable bit. 1=enable, 0=disable bit 6 - 0 device id bit 6* bit 5 - 0 watchdog time interval bit 5 (msb) device id bit 5* bit 4 - 0 watchdog time interval bit 4 device id bit 4* bit 3 - 0 watchdog time interval bit 3 device id bit 3* bit 2 - 0 watchdog time interval bit 2 device id bit 2* bit 1 - 1 watchdog time interval bit 1 device id bit 1* bit 0 - 1 watchdog time interval bit 0 (lsb) device id bit 0* note: *: default value at power-up
PLL205-13 motherboard clock generator for amd - k7 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 06/23/00 page 8 programming of cpu frequency to simplify traditional loop counter setting, the PLL205-13 device incorporates smart-byte ? technology with a single byte programming via i2c to better optimize clock jitter and spread spectrum performance. detail of PLL205-13's dual mode frequency programming method is described below: 1. rom-table frequency programming: the pre-defined 32 frequencies found in frequency table can be accessed either through 5 external jumpers or by setting internal i2c register in byte0. 2. micro-step linear frequency programming: cpu frequency can be programmed via i2c in fine and linear positive or negative stepping around selected cpu frequency in frequency table. the highest step is either +127 or -127. other bus frequencies will be changed proportionally with the rate that cpu frequency change. the formula is as follow: f cpu = f cpu.rom-table a a (=0.22) * m where: 1. m is magnitude factor defined in i2c byte 7.bit(0:6) 2. ( sign bit) of m is defined in i2c byte7.bit 7 3. a is a constant a = 0.22 frequency programming example: 1. procedures to program target cpu frequency to 139.0 mhz: a. locate the closest cpu frequency from frequency-rom table: 136.5 b. a = 0.22 c. solve m (linear magnitude factor) in integer: m = (f cpu - f cpu - romtable ) / a = (139 ? 136.5) / 0.22 = 11 d. program i2c register: 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 fs3 fs2 fs1 fs0 ctr fs4 7 6 5 4 3 2 1 0 0 0 0 0 1 0 1 1 sign m6 m5 m4 m3 m2 m1 m0 f cpu = 136.5 + (0.22) * 11 = 138.92 ( % of frequency increased = 1.8 % ) f pci = 34.1 * (1+1.8%) = 34.7 setting of m = +11 in i2c.byte7 setting of i2c.byte0
PLL205-13 motherboard clock generator for amd - k7 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 06/23/00 page 9 built-in watchdog timer (wdt) watchdog timer is used to perform safe recovery if frequency switching causes system to enter into ?hang-up? state within a reasonable period of time (or watchdog time interval). while disabled, the watchdog time interval can be programmed between 0 and 63 seconds with increment of 1 second by setting the value of i2c.byte8.bit(5:0). once enabled, wdt has to be disabled within a period that is shorter than the programmed watchdog interval; otherwise wdt will generate a 500ms low watchdog reset pulse to provoke a system reset. after system restarts, the PLL205-13 will start from predefined fall-back frequency (the value of i2c byte6 ,bits(7:3)). if system for any reason fails again at fall-back frequency, the internal hardware will then generate a watchdog reset to restart the system from the value of external hardware jumper setting to ensure a safe recovery. example usage: 1. system power-up at cpu= 66.8mhz where external jumpers are used. 2a. switch to target cpu=100.0mhz frequency with following i2c register setting: 7 6 5 4 3 2 1 0 0 0 1 1 1 0 0 0 fs3 fs2 fs1 fs0 ctr fs4 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 sign m6 m5 m4 m3 m2 m1 m0 7 6 5 4 3 2 1 0 1 0 0 0 1 1 1 1 enb t5 t4 t3 t2 t1 t0 7 6 5 4 3 2 1 0 0 0 0 1 1 0 0 0 fb4 fb3 fb2 fb1 fb0 the fall-back frequency is set to the same location as that of fsel since frequency switching between different timing groups will cause system to hang up. after wd timer expired or 15 seconds, the system will restart properly at target 100.0mhz if cpu is capable; otherwise wdt will perform another reset action to restart the system from 66.8 mhz 2b. switch to target cpu=78mhz within the same timing group the fall-back frequency is recommended to set at the most safe and comfortable level to ensure a successful reboot such as 70 or 75.3 if system is unable to switch to 78mhz. fsel setting in i2c.byte0 m =0 setting in i2c.byte7 wd-timer = 15s setting in i2c.byte8 fbsel setting in i2c.byte6
PLL205-13 motherboard clock generator for amd - k7 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 06/23/00 page 10 success i2c register loading: fall-back, m, wd-timer , wd-enable i2c register loading: fsel wait for system response fail - after specified wd-timer expired disable wd- enable bit f cpu = target setting system restart @ fall-back frequency fail - after specified wd-timer expired success copy fall-back frequency setting to i2c frequency setting disable wd- enable bit f cpu = fall-back frequency setting system restart @ jumper-setting frequency end start end end wdt operational flow chart
PLL205-13 motherboard clock generator for amd - k7 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 06/23/00 page 11 electrical specifications 1. absolute maximum ratings parameters symbol min. max. units supply voltage v dd v ss - 0.5 7 v input voltage, dc v i v ss - 0.5 v dd + 0.5 v output voltage, dc v o v ss - 0.5 v dd + 0.5 v storage temperature t s -65 150 c ambient operating temperature t a 0 70 c junction temperature t j 115 c esd voltage 2 kv exposure of the device under conditions beyond the limits specified by maximum ratings for extended periods may cause permanent damage to the device and affect product reliability. these conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. 2. ac/dc electrical specifications parameters symbol conditions min. typ. max. units input high voltage v ih 2.0 v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd 5 m a input low current i il1 logic inputs without internal pull-up on sclk, v in = 0v -5 m a input low current i il2 logic inputs with internal pull-up resistors, v in = 0v -200 m a power down pd 600 m a pull-up resistor r pu pin 2,7,8,10,25,26,48 120 kohm c l =0 pf @ 66mhz c l =0 pf @ 100mhz operating supply current i dd c l =0 pf @ 133mhz 180 ma input frequency f i v dd = 3.3v 12 14.318 16 mhz c in logic inputs 5 pf input capacitance c inx xin & xout pins 27 45 pf
PLL205-13 motherboard clock generator for amd - k7 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 06/23/00 page 12 2. output buffer electrical specifications unless otherwise stated, all power supplies = 3.3v 5%, and ambient temperature range t a = 0 c to 70 c parameters symbol outputs conditions min. typ. max. units cput1 measured @ 0.3v ~ 1.2v, c l =20pf, 3.3v 5% 2 cpu (open drain) measured @ 0.3v ~ 1.2v, c l =20pf, 3.3v 5% 0.9 ref(0:1) measured @ 0.4v ~ 2.4v, c l =20pf, 3.3v 5% 4 pci(0:5) measured @ 0.4v ~ 2.4v, c l =30pf, 3.3v 5% 2 output rise time t or 24_48mhz, 48mhz measured @ 0.4v ~ 2.4v, c l =20pf, 3.3v 5% 4 ns cput1 measured @ 0.3v ~ 1.2v, c l =20pf, 3.3v 5% 2 cpu (open drain) measured @ 1.2v ~ 0.3v, c l =20pf, 3.3v 5% 0.9 ref(0:1) measured @ 2.4v ~ 0.4v, c l =20pf, 3.3v 5% 4 pci(0:5) measured @ 2.4v ~ 0.4v, c l =30pf, 3.3v 5% 2 output fall time t of 24_48mhz, 48mhz measured @ 2.4v ~ 0.4v, c l =20pf, 3.3v 5% 4 ns ref(0:1),cpu, pci(0:5) v t = 50% duty cycle d t 24_48mhz, 48mhz v t = 1.5v 45 55 % cput1 to cput0 200 pci to pci 200 ps cpu to pci 0 3 clock skew t skew cpu to agp v t = 50% -500 500 ns cput1 30 cpu v o = v x 50 pci(0:5) 30 ref(0:1) 40 ref1 40 output impedance z 0 24_48mhz, 48mhz v dd =3.3v 5% 40 ohm
PLL205-13 motherboard clock generator for amd - k7 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 06/23/00 page 13 2. output buffer electrical specifications, continued unless otherwise stated, all power supplies = 3.3v 5%, and ambient temperature range t a = 0 c to 70 c parameters symbol outputs conditions min. typ. max. units cput1 -40 cpu -40 ref(0:1) -34 pci(0:5) -34 24_48mhz -34 48mhz -34 output high current i oh sdram v oh = 2.0v -55 ma cput1 20 cpu v ol = 0.4v 20 ref(0:1) 25 pci(0:5) 25 24_48mhz 25 48mhz 25 output low current i ol sdram v ol = 0.8v 43 ma jitter, one sigma j sigma ref,48mhz,24mhz v t = 1.5v 0.5 ns cpu v t = 50% -250 250 ps jitter, absolute j abs ref,48mhz,24mhz v t = 1.5v -1 1 ns cpu v t = v x 250 jitter (cycle to cycle) j cyc-cyc pci measured @ 1.5v 250 ps ac differential voltage v dif 0.4 v pullup +0.6 v dc differential voltage v dif 0.2 v pullup +0.6 v differential crossover voltage v x cpu (open drain) 550 1100 mv note: v pullup = 1.5v (external); v dif specifies the minimum input differential voltages (v tr -v cp ) required for switching, where v tr is the ?true? input level and v cp is the ?complement? input level.
PLL205-13 motherboard clock generator for amd - k7 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 06/23/00 page 14 package information ordering information phaselink corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. the information furnished by phaselink is believed to be accurate and reliable. however, phaselink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. life support policy : phaselink?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of phaselink corporation. for part ordering, please contact our sales department: 47745 fremont blvd., fremont, ca 94538, usa tel: (510) 492-0990 fax: (510) 492-0991 part number the order number for this device is a combination of the following: device number, package type and operating temperature range PLL205-13 x c part number temperaturature c=commercial m=military i=industral package type x=ssop 0.008 - 0.016 (0.203 - 0.406) 0.620 - 0.630 (15.75 - 16.00) (0.254 - 0.406) 45 0 0.010 - 0.016 0.050 (1.27) min 3 0 -6 0 0.015 (0.381) 0.088 - 0.096 (2.235 - 2.438) 0.097 - 0.104 (2.464 - 2.642) 0.025 0.635 0.400 - 0.410 10.160 - 10.414 0.292 - 0.299 7.417 - 7.595 0.008 - 0.0135 0.203 - 0.343 48pin ssop

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